Conventionally, metal oxide semiconductor field effect transistors (MOSFET) are fabricated by forming field isolation layers in a semiconductor substrate to define a plurality of active regions. Shallow trench isolation (STI) techniques are often used to form the field isolation layers. When an STI technique is used, trench mask patterns are formed on the semiconductor substrate. The trench mask patterns are then used as an etch mask in an anisotropic etch process to form trenches at the semiconductor substrate that are then filled to form the field isolation layers.
In the case of forming a non-volatile memory cell, control gate electrodes (or gate electrodes) are formed to cross over the respective active regions with floating gate electrodes disposed thereunder. The process used to form the floating gate electrodes generally includes two patterning processes. The first patterning process employs a mask pattern that runs in parallel to the active region. The second patterning process uses a mask pattern that runs in a vertical direction to the active region which may be used to form the gate electrodes.
However, the patterning process that uses a mask pattern that runs in a parallel direction to the active region requires an additional mask pattern. Thus, in order to form the floating gate electrodes, a photolithography process should additionally be performed. In this photolithography process, process parameters such as the width that the floating gate electrode overlap each edge of the field isolation layer and the “overlap symmetry” (i.e., the symmetry with which the floating gate electrode overlaps the field isolation layer) are strictly controlled. However, as semiconductor devices become more highly integrated, it can become difficult to strictly control these process parameters, and the cost of the photolithography process may be relatively high.